The emergence of mobile consumer electronics, such as cellular telephones, laptop computers, Personal Digital Assistants (PDAs), and MP3 players, has increased the demand for compact, high performance memory devices. These memory devices are subject to increasingly stringent constraints in terms of the number of data bits that can be provided at defined operating speeds using the smallest possible device. In this context, the term “smallest” generally refers to the lateral area occupied by the memory device in a “lateral” X/Y plane, such as a plane defined by the primary surfaces of a printed circuit board or module board.
As a result of the constraints on the area occupied by the device, microchip designers have begun to vertically integrate the data storage capacity of their devices. Thus, multiple memory devices that might have previously been laid out adjacent to one another in a lateral plane are now vertically stacked one on top of the other in a Z plane relative to the lateral X/Y plane, thereby greatly increasing the memory density per area that the device occupies on the board.
Recent developments in the fabrication of through silicon vias (TSVs) have facilitated the trend towards vertically stacked semiconductor memory devices, by providing more efficient communication between stacked chips and by further reducing the area occupied by the device. Most 3-D stacked technologies have focused on only chip-level integration in the vertical direction. One performance bottleneck results from the speed difference between the increasingly-fast microprocessor and the relatively fixed latency times of the main memory (typically DRAM). In order to mitigate this performance bottleneck, the memory I/O interface has been improved in an attempt to keep pace with ever-accelerating CPU performance. However, another limiting factor is the distance between the CPU and the memory, which contributes to signal distortion and degradation of signal integrity, and increases power consumption by the I/O signal connection. The distance between the CPU and the memory device is limited by the physical dimensions of memory and the CPU if these devices are both mounted next to each other on the same board. This distance can be reduced by stacking memory devices with the CPU. Two common stacking arrangements are memory over CPU (FIG. 1) and CPU over memory (FIG. 2). The arrangement of FIG. 1 has disadvantages in terms of heat dissipation, because the heat from the CPU must be conducted through the DRAM stack to reach the heat sink. However, the arrangement of FIG. 2 requires the CPU to communicate to external devices (via the board) using TSVs through the intervening DRAM stack, thereby increasing the TSV overhead of the DRAM stack and reducing storage capacity accordingly.
The processor cores of the CPU chip consume a lot of power and generate heat during normal operation. It is not atypical for the processor cores of the CPU chip to generate hot spots about 30° C. (about 55° F.) hotter than the cooler portions of the chip such as the area allocated to the level 2 (L2) SRAM cache. This high temperature can adversely affect the performance of adjacent DRAM devices, which are inherently temperature-sensitive, and which themselves consume a significant amount of power during operation. Higher temperatures contribute to degradation of memory performance, require more frequent refresh cycles, and increase power consumption in DRAM devices. The stacked arrangement exacerbates the heat dissipation problem, because multiple heat-generating dies are in close proximity and must share a heat sink. Thermal issues are one limiting factor in the maximum acceptable height of the DRAM stack, thereby limiting the memory capacity available to the CPU, as well as adversely affecting the proper operation of the DRAM chips provided.
One approach to regulating thermal issues is to configure the CPU so that the hot spots are more evenly distributed over the area occupied by the processor cores. However, this increases design complexity and may conflict with optimized logic block placement in the CPU. In addition, this approach is of limited benefit when the CPU and the DRAM are stacked together, because the DRAM is still exposed to the same quantity of heat overall.
Therefore, there is a need to provide a stacked arrangement of a CPU and a DRAM memory wherein the stacked DRAM memory is exposed to reduced thermal effects.
There is also a need to provide a stacked arrangement of a CPU and a DRAM memory having efficient heat dissipation.